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# OpenOCD
# OpenOCD Binaries
## Getting started
To make it easy for you to get started with GitLab, here's a list of recommended next steps.
Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)!
## Add your files
- [ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files
- [ ] [Add files using the command line](https://docs.gitlab.com/ee/gitlab-basics/add-file.html#add-a-file-using-the-command-line) or push an existing Git repository with the following command:
```
cd existing_repo
git remote add origin https://gitlab.tugraz.at/microcontroller/openocd.git
git branch -M main
git push -uf origin main
```
## Integrate with your tools
- [ ] [Set up project integrations](https://gitlab.tugraz.at/microcontroller/openocd/-/settings/integrations)
## Collaborate with your team
- [ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/)
- [ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html)
- [ ] [Automatically close issues from merge requests](https://docs.gitlab.com/ee/user/project/issues/managing_issues.html#closing-issues-automatically)
- [ ] [Enable merge request approvals](https://docs.gitlab.com/ee/user/project/merge_requests/approvals/)
- [ ] [Set auto-merge](https://docs.gitlab.com/ee/user/project/merge_requests/merge_when_pipeline_succeeds.html)
## Test and Deploy
Use the built-in continuous integration in GitLab.
- [ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/index.html)
- [ ] [Analyze your code for known vulnerabilities with Static Application Security Testing (SAST)](https://docs.gitlab.com/ee/user/application_security/sast/)
- [ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html)
- [ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/)
- [ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html)
***
# Editing this README
When you're ready to make this README your own, just edit this file and use the handy template below (or feel free to structure it however you want - this is just a starting point!). Thanks to [makeareadme.com](https://www.makeareadme.com/) for this template.
## Suggestions for a good README
Every project is different, so consider which of these sections apply to yours. The sections used in the template are suggestions for most open source projects. Also keep in mind that while a README can be too long and detailed, too long is better than too short. If you think your README is too long, consider utilizing another form of documentation rather than cutting out information.
## Name
Choose a self-explaining name for your project.
## Description
Let people know what your project can do specifically. Provide context and add a link to any reference visitors might be unfamiliar with. A list of Features or a Background subsection can also be added here. If there are alternatives to your project, this is a good place to list differentiating factors.
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## Usage
Use examples liberally, and show the expected output if you can. It's helpful to have inline the smallest example of usage that you can demonstrate, while providing links to more sophisticated examples if they are too long to reasonably include in the README.
## Support
Tell people where they can go to for help. It can be any combination of an issue tracker, a chat room, an email address, etc.
## Roadmap
If you have ideas for releases in the future, it is a good idea to list them in the README.
## Contributing
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For people who want to make changes to your project, it's helpful to have some documentation on how to get started. Perhaps there is a script that they should run or some environment variables that they need to set. Make these steps explicit. These instructions could also be useful to your future self.
You can also document commands to lint the code or run tests. These steps help to ensure high code quality and reduce the likelihood that the changes inadvertently break something. Having instructions for running tests is especially helpful if it requires external setup, such as starting a Selenium server for testing in a browser.
## Authors and acknowledgment
Show your appreciation to those who have contributed to the project.
## License
For open source projects, say how it is licensed.
## Project status
If you have run out of energy or time for your project, put a note at the top of the README saying that development has slowed down or stopped completely. Someone may choose to fork your project or volunteer to step in as a maintainer or owner, allowing your project to keep going. You can also make an explicit request for maintainers.
Custom-built OpenOCD binaries for Raspberry PI Pico development on Windows.
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# SPDX-License-Identifier: GPL-2.0-or-later
#----------------------------------------
# Purpose - Create some $BIT variables
# Create $K and $M variables
# and some bit field extraction variables.
# Create helper variables ...
# BIT0.. BIT31
for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} {
set vn [format "BIT%d" $x]
global $vn
set $vn [expr {1 << $x}]
}
# Create K bytes values
# __1K ... to __2048K
for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} {
set vn [format "__%dK" $x]
global $vn
set $vn [expr {1024 * $x}]
}
# Create M bytes values
# __1M ... to __2048K
for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} {
set vn [format "__%dM" $x]
global $vn
set $vn [expr {1024 * 1024 * $x}]
}
proc create_mask { MSB LSB } {
return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}]
}
# Cut Bits $MSB to $LSB out of this value.
# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
# Result: 0x02340000
proc extract_bitfield { VALUE MSB LSB } {
return [expr {[create_mask $MSB $LSB] & $VALUE}]
}
# Cut bits $MSB to $LSB out of this value
# and shift (normalize) them down to bit 0.
#
# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
# Result: 0x00000234
#
proc normalize_bitfield { VALUE MSB LSB } {
return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}]
}
proc show_normalize_bitfield { VALUE MSB LSB } {
set m [create_mask $MSB $LSB]
set mr [expr {$VALUE & $m}]
set sr [expr {$mr >> $LSB}]
echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
return $sr
}
# SPDX-License-Identifier: GPL-2.0-or-later
# Product page:
# https://www.8devices.com/products/lima
#
# Location of JTAG pins:
# J2 GPIO0 JTAG TCK
# J2 GPIO1 JTAG TDI
# J2 GPIO2 JTAG TDO
# J2 GPIO3 JTAG TMS
# J2 RST directly connected to RESET_L of the SoC and can be used as
# JTAG SRST. Note: this pin will also reset the debug engine.
# J1 +3,3V Can be use as JTAG Vref
# J1 or J2 GND Can be used for JTAG GND
#
# This board is powered from mini USB connecter which is also used
# as USB to UART converted based on FTDI FT230XQ chip
source [find target/qualcomm_qca4531.cfg]
proc board_init { } {
qca4531_ddr2_550_550_init
}
$_TARGETNAME configure -event reset-init {
board_init
}
set ram_boot_address 0xa0000000
$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
# SPDX-License-Identifier: GPL-2.0-or-later
# board config file for AcTux3/XBA IXP42x board
# Date: 2010-12-16
# Author: Michael Schwingen <michael@schwingen.org>
reset_config trst_and_srst separate
adapter srst delay 100
jtag_ntrst_delay 100
source [find target/ixp42x.cfg]
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
$_TARGETNAME configure -event reset-init { init_actux3 }
proc init_actux3 { } {
##########################################################################
# setup expansion bus CS
##########################################################################
mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
mww 0xc4000004 0x94d10013 ;#CS1
mww 0xc4000008 0x95960003 ;#CS2
mww 0xc400000c 0x00000000 ;#CS3
mww 0xc4000010 0x80900003 ;#CS4
mww 0xc4000014 0x9d520003 ;#CS5
mww 0xc4000018 0x81860001 ;#CS6
mww 0xc400001c 0x80900003 ;#CS7
ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
#mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
ixp42x_set_bigendian
flash probe 0
}
proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
echo "writing bootloader: $FILE"
flash write_image erase $FILE 0x50000000 bin
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
init
reset init
# setup to debug u-boot in flash
proc uboot_debug {} {
gdb_breakpoint_override hard
xscale vector_catch 0xFF
xscale vector_table low 1 0xe59ff018
xscale vector_table low 2 0xe59ff018
xscale vector_table low 3 0xe59ff018
xscale vector_table low 4 0xe59ff018
xscale vector_table low 5 0xe59ff018
xscale vector_table low 6 0xe59ff018
xscale vector_table low 7 0xe59ff018
xscale vector_table high 1 0xe59ff018
xscale vector_table high 2 0xe59ff018
xscale vector_table high 3 0xe59ff018
xscale vector_table high 4 0xe59ff018
xscale vector_table high 5 0xe59ff018
xscale vector_table high 6 0xe59ff018
xscale vector_table high 7 0xe59ff018
}
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Adapteva Parallella-I board (via Porcupine-1 adapter board)
#
reset_config srst_only
source [find target/zynq_7000.cfg]
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Analog Devices ADSP-SC584-EZBRD evaluation board
#
# Evaluation boards by Analog Devices (and designs derived from them) use a
# non-standard 10-pin 0.05" ARM Cortex Debug Connector. In this bastardized
# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.
#
# As a result, a standards-compliant debug pod will force /TRST active,
# putting the processor's debug interface into reset and preventing usage.
#
# A connector adapter must be employed on these boards to isolate or remap
# /TRST so that it is only asserted when intended.
# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with all
# ADSP-SC58x designs, but this is an ARM target (and subject to the
# qualifications above) many ARM debug pods should be compatible.
#source [find interface/cmsis-dap.cfg]
source [find interface/jlink.cfg]
# Analog's silicon supports SWD and JTAG, but their proprietary ICE is limited
# to JTAG. (This is presumably why their connector pinout was modified.)
# SWD is chosen here, as it is more efficient and doesn't require /TRST.
transport select swd
# chosen speed is 'safe' choice, but your adapter may be capable of more
adapter speed 400
source [find target/adsp-sc58x.cfg]
# SPDX-License-Identifier: GPL-2.0-or-later
source [find target/alphascale_asm9260t.cfg]
reset_config trst_and_srst
$_TARGETNAME configure -event reset-init {
echo "Configure clock"
# Enable SRAM clk
mww 0x80040024 0x4
# Enable IRQ clk
mww 0x80040034 0x100
# Enable DMA0,1 clk
mww 0x80040024 0x600
# Make sysre syspll is enabled
mww 0x80040238 0x750
#CPU = PLLCLK/2
mww 0x8004017C 0x2
#SYSAHBCLK = CPUCLK/2
mww 0x80040180 0x2
# Set PLL freq to 480MHz
mww 0x80040100 480
# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
sleep 100
# select PLL as main source
mww 0x80040120 0x1
# disable and enable main clk to update changes?
mww 0x80040124 0x0
mww 0x80040124 0x1
echo "Configure memory"
#enable EMI CLK
mww 0x80040024 0x40
# configure memory controller for internal SRAM
mww 0x80700000 0x1188
# change default emi clk delay
mww 0x8004034C 0xA0503
# make sure chip_select_register2_low has correct value (why?)
mww 0x8070001c 0x20000000
# set type to sdram and size to 32MB
mww 0x8070005c 0xa
# configure internal SDRAM timing
mww 0x80700004 0x024996d9
# configure Static Memory timing
mww 0x80700094 0x00542b4f
echo "Configure uart4"
# enable pinctrl clk
mww 0x80040024 0x2000000
# mux GPIO3_0 and GPIO3_1 to UART4
mww 0x80044060 0x2
mww 0x80044064 0x2
# configure UART4CLKDIV
mww 0x800401a8 0x1
# enable uart4 clk
mww 0x80040024 0x8000
# clear softrst and clkgate on uart4
mww 0x80010008 0xC0000000
# set bandrate 115200 12M
mww 0x80010030 0x00062070
# enable Rx&Tx
mww 0x80010024 0x301
# clear hw control
mww 0x80010028 0xc000
}
$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
$_TARGETNAME arm7_9 fast_memory_access enable
$_TARGETNAME arm7_9 dcc_downloads enable
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Cyclone V SocKit board
# http://www.altera.com/b/arrow-sockit.html
#
# Software support page:
# http://www.rocketboards.org/
# openocd does not currently support the on-board USB Blaster II.
# Install the JTAG header and use a USB Blaster instead.
adapter driver usb_blaster
source [find target/altera_fpgasoc.cfg]
# If the USB Blaster II were supported, these settings would be needed
#usb_blaster vid_pid 0x09fb 0x6810
#usb_blaster device_desc "USB-Blaster II"
adapter speed 100
# SPDX-License-Identifier: GPL-2.0-or-later
# DANGER!!!! early work in progress for this PCB/target.
#
# The most basic operations work well enough that it is
# useful to have this in the repository for cooperation
# alpha testing purposes.
#
# TI AM3517
#
# http://focus.ti.com/docs/prod/folders/print/am3517.html
# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
set CHIPTYPE "am35x"
source [find target/amdm37x.cfg]
# The TI-14 JTAG connector does not have srst. CPU reset is handled in
# hardware.
reset_config trst_only
# "amdm37x_dbginit am35x.cpu" needs to be run after init.
# SPDX-License-Identifier: GPL-2.0-or-later
#
# OpenOCD Board Configuration for eMAG Development Platform
#
# Copyright (c) 2019-2021, Ampere Computing LLC
#
#
# Configure JTAG speed
#
adapter speed 2000
#
# Configure Resets
#
jtag_ntrst_delay 100
reset_config trst_only
#
# Configure Targets
#
source [find target/ampere_emag.cfg]
# SPDX-License-Identifier: GPL-2.0-or-later
#
# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
# Ampere Altra Max ("Mystique") processors
#
# Copyright (c) 2019-2021, Ampere Computing LLC
# Argument Description
#
# JTAGFREQ
# Set the JTAG clock frequency
# Syntax: -c "set JTAGFREQ {freq_in_khz}"
#
# SYSNAME
# Set the system name
# If not specified, defaults to "qs"
# Syntax: -c "set SYSNAME {qs}"
#
# Life-Cycle State (LCS)
# If not specified, defaults to "Secure LCS"
# LCS=0, "Secure LCS"
# LCS=1, "Chip Manufacturing LCS"
# Syntax: -c "set LCS {0}"
# Syntax: -c "set LCS {1}"
#
# CORELIST_S0
# Specify available physical cores by number
# Example syntax to connect to physical cores 16 and 17 for S0
# Syntax: -c "set CORELIST_S0 {16 17}"
#
# COREMASK_S0_LO
# Specify available physical cores 0-63 by mask
# Example syntax to connect to physical cores 16 and 17 for S0
# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
#
# COREMASK_S0_HI
# Specify available physical cores 64 and above by mask
# Example syntax to connect to physical cores 94 and 95 for S0
# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
#
# PHYS_IDX
# Enable OpenOCD ARMv8 core target physical indexing
# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
# Syntax: -c "set PHYS_IDX {}"
#
# Configure JTAG speed
#
if { [info exists JTAGFREQ] } {
adapter speed $JTAGFREQ
} else {
adapter speed 100
}
#
# Set the system name
#
if { [info exists SYSNAME] } {
set _SYSNAME $SYSNAME
} else {
set _SYSNAME qs
}
#
# Configure Resets
#
jtag_ntrst_delay 100
reset_config trst_only
#
# Configure Targets
#
if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {
set CHIPNAME ${_SYSNAME}0
if { [info exists CORELIST_S0] } {
set CORELIST $CORELIST_S0
} else {
if { [info exists COREMASK_S0_LO] } {
set COREMASK_LO $COREMASK_S0_LO
} else {
set COREMASK_LO 0x0
}
if { [info exists COREMASK_S0_HI] } {
set COREMASK_HI $COREMASK_S0_HI
} else {
set COREMASK_HI 0x0
}
}
} else {
set CHIPNAME ${_SYSNAME}0
set COREMASK_LO 0x1
set COREMASK_HI 0x0
}
source [find target/ampere_qs_mq.cfg]
# SPDX-License-Identifier: GPL-2.0-or-later
#
# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
# Ampere Altra Max ("Mystique") processors
#
# Copyright (c) 2019-2021, Ampere Computing LLC
# Argument Description
#
# JTAGFREQ
# Set the JTAG clock frequency
# Syntax: -c "set JTAGFREQ {freq_in_khz}"
#
# SYSNAME
# Set the system name
# If not specified, defaults to "qs"
# Syntax: -c "set SYSNAME {qs}"
#
# Life-Cycle State (LCS)
# If not specified, defaults to "Secure LCS"
# LCS=0, "Secure LCS"
# LCS=1, "Chip Manufacturing LCS"
# Syntax: -c "set LCS {0}"
# Syntax: -c "set LCS {1}"
#
# CORELIST_S0, CORELIST_S1
# Specify available physical cores by number
# Example syntax to connect to physical cores 16 and 17 for S0 and S1
# Syntax: -c "set CORELIST_S0 {16 17}"
# Syntax: -c "set CORELIST_S1 {16 17}"
#
# COREMASK_S0_LO, COREMASK_S1_LO
# Specify available physical cores 0-63 by mask
# Example syntax to connect to physical cores 16 and 17 for S0 and S1
# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
#
# COREMASK_S0_HI, COREMASK_S1_HI
# Specify available physical cores 64 and above by mask
# Example syntax to connect to physical cores 94 and 95 for S0 and S1
# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
#
# SPLITSMP
# Group all ARMv8 cores per socket into individual SMP sessions
# If not specified, group ARMv8 cores from both sockets into one SMP session
# Syntax: -c "set SPLITSMP {}"
#
# PHYS_IDX
# Enable OpenOCD ARMv8 core target physical indexing
# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
# Syntax: -c "set PHYS_IDX {}"
#
# Configure JTAG speed
#
if { [info exists JTAGFREQ] } {
adapter speed $JTAGFREQ
} else {
adapter speed 100
}
#
# Set the system name
#
if { [info exists SYSNAME] } {
set _SYSNAME $SYSNAME
} else {
set _SYSNAME qs
}
#
# Configure Board level SMP configuration if necessary
#
if { ![info exists SPLITSMP] } {
# Group dual chip into a single SMP configuration
set SMP_STR "target smp"
set CORE_INDEX_OFFSET 0
set DUAL_SOCKET_SMP_ENABLED ""
}
#
# Configure Resets
#
jtag_ntrst_delay 100
reset_config trst_only
#
# Configure Targets
#
if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
[info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
set CHIPNAME ${_SYSNAME}1
if { [info exists CORELIST_S1] } {
set CORELIST $CORELIST_S1
} else {
if { [info exists COREMASK_S1_LO] } {
set COREMASK_LO $COREMASK_S1_LO
} else {
set COREMASK_LO 0x0
}
if { [info exists COREMASK_S1_HI] } {
set COREMASK_HI $COREMASK_S1_HI
} else {
set COREMASK_HI 0x0
}
}
source [find target/ampere_qs_mq.cfg]
if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
if { [info exists MQ_ENABLE] } {
set CORE_INDEX_OFFSET 128
} else {
set CORE_INDEX_OFFSET 80
}
}
set CHIPNAME ${_SYSNAME}0
if { [info exists CORELIST_S0] } {
set CORELIST $CORELIST_S0
} else {
if { [info exists COREMASK_S0_LO] } {
set COREMASK_LO $COREMASK_S0_LO
} else {
set COREMASK_LO 0x0
}
if { [info exists COREMASK_S0_HI] } {
set COREMASK_HI $COREMASK_S0_HI
} else {
set COREMASK_HI 0x0
}
}
source [find target/ampere_qs_mq.cfg]
} else {
set CHIPNAME ${_SYSNAME}1
set COREMASK_LO 0x0
set COREMASK_HI 0x0
source [find target/ampere_qs_mq.cfg]
if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
if { [info exists MQ_ENABLE] } {
set CORE_INDEX_OFFSET 128
} else {
set CORE_INDEX_OFFSET 80
}
}
set CHIPNAME ${_SYSNAME}0
set COREMASK_LO 0x1
set COREMASK_HI 0x0
source [find target/ampere_qs_mq.cfg]
}
if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
# For dual socket SMP configuration, evaluate the string
eval $SMP_STR
}
# SPDX-License-Identifier: GPL-2.0-or-later
# This board is from ARM and has an samsung s3c45101x01 chip
source [find target/samsung_s3c4510.cfg]
#
# FIXME:
# Add (A) sdram configuration
# Add (B) flash cfi programming configuration
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Configuration script for ARM Musca-A development board
#
# For now we do not support Musca A flash programming using OpenOCD. However, a
# work area is configured for flash programming speed up.
#
# GDB considers all memory as RAM unless target supplies a memory map.
# OpenOCD will only send memory map if flash banks are configured. Otherwise,
# configure GDB after connection by issuing following commands:
# (gdb) mem 0x10200000 0x109FFFFF ro
# (gdb) mem 0x00200000 0x009FFFFF ro
# (gdb) set mem inaccessible-by-default off
# ARM Musca A board supports both JTAG and SWD transports.
source [find target/swj-dp.tcl]
# set a safe JTAG clock speed, can be overridden
adapter speed 1000
global _CHIPNAME
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME MUSCA_A
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x6ba00477
}
# Enable CPU1 debugging as a separate GDB target
set _ENABLE_CPU1 1
# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU
set WORKAREASIZE_CPU0 0x2000
set WORKAREASIZE_CPU1 0x2000
# Set SRAM bank 1 to be used for work area. Override here if needed.
set WORKAREAADDR_CPU0 0x30008000
set WORKAREAADDR_CPU1 0x3000A000
source [find target/arm_corelink_sse200.cfg]
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists
#
# https://www.xilinx.com/products/boards-and-kits/1-pnziih.html
# https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-makers-and-hobbyists/
source [find interface/ftdi/digilent-hs1.cfg]
# Xilinx Spartan7-25/50 FPGA (XC7S{25,50}-CSGA324)
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
adapter speed 25000
# Usage:
#
# Load Bitstream into FPGA:
# openocd -f board/arty_s7.cfg -c "init;\
# pld load 0 bitstream.bit;\
# shutdown"
#
# Write Bitstream to Flash:
# openocd -f board/arty_s7.cfg -c "init;\
# jtagspi_init 0 bscan_spi_xc7s??.bit;\
# jtagspi_program bitstream.bin 0;\
# xc7_program xc7.tap;\
# shutdown"
#
# jtagspi flash proxies can be found at:
# https://github.com/quartiq/bscan_spi_bitstreams
#
# For the Spartan 50 variant, use
# - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s50.bit
# For the Spartan 25 variant, use
# - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s25.bit
# SPDX-License-Identifier: GPL-2.0-or-later
#
# http://wikidevi.com/wiki/ASUS_RT-N16
#
set partition_list {
CFE { Bootloader 0xbc000000 0x00040000 }
firmware { "Kernel+rootfs" 0xbc040000 0x01fa0000 }
nvram { "Config space" 0xbdfe0000 0x00020000 }
}
source [find target/bcm4718.cfg]
# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q)
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8
# SPDX-License-Identifier: GPL-2.0-or-later
#
# http://wikidevi.com/wiki/Asus_RT-N66U
#
echo "ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC"
echo "to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ,"
echo "there is an unpopulated footprint near U8.\n"
set partition_list {
CFE { Bootloader 0xbc000000 0x00040000 }
firmware { "Kernel+rootfs" 0xbc040000 0x01fa0000 }
nvram { "Config space" 0xbdfe0000 0x00020000 }
}
source [find target/bcm4706.cfg]
# External 32MB NOR Flash (Spansion S29GL256P10TF101
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME
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